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CASES
2010
ACM
15 years 4 months ago
Fine-grain dynamic instruction placement for L0 scratch-pad memory
We present a fine-grain dynamic instruction placement algorithm for small L0 scratch-pad memories (spms), whose unit of transfer can be an individual instruction. Our algorithm ca...
JongSoo Park, James D. Balfour, William J. Dally
158
Voted
DAC
2009
ACM
16 years 7 months ago
A DVS-based pipelined reconfigurable instruction memory
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
Zhiguo Ge, Tulika Mitra, Weng-Fai Wong
IPPS
2008
IEEE
16 years 18 days ago
Performance characterization and optimization of parallel I/O on the Cray XT
This paper presents an extensive characterization, tuning, and optimization of parallel I/O on the Cray XT supercomputer, named Jaguar, at Oak Ridge National Laboratory. We have c...
Weikuan Yu, Jeffrey S. Vetter, Sarp Oral
CLUSTER
2009
IEEE
15 years 10 months ago
Analytical modeling and optimization for affinity based thread scheduling on multicore systems
Abstract--This paper proposes an analytical model to estimate the cost of running an affinity-based thread schedule on multicore systems. The model consists of three submodels to e...
Fengguang Song, Shirley Moore, Jack Dongarra
ISCA
1997
IEEE
137views Hardware» more  ISCA 1997»
15 years 10 months ago
VM-Based Shared Memory on Low-Latency, Remote-Memory-Access Networks
Recent technological advances have produced network interfaces that provide users with very low-latency access to the memory of remote machines. We examine the impact of such netw...
Leonidas I. Kontothanassis, Galen C. Hunt, Robert ...