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VLSID
2007
IEEE
108views VLSI» more  VLSID 2007»
14 years 10 months ago
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET mode...
Feng Wang 0004, Yuan Xie, R. Rajaraman, Balaji Vai...
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
14 years 3 months ago
Implicit and Exact Path Delay Fault Grading in Sequential Circuits
1 The first path implicit and exact non–robust path delay fault grading technique for non–scan sequential circuits is presented. Non enumerative exact coverage is obtained, b...
Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, S...
ICCV
1999
IEEE
14 years 2 months ago
Geodesic Active Regions for Supervised Texture Segmentation
This paper presents a novel variational method for supervised texture segmentation. The textured feature space is generated by filtering the given textured images using isotropic ...
Nikos Paragios, Rachid Deriche
DATE
1998
IEEE
121views Hardware» more  DATE 1998»
14 years 2 months ago
Fuzzy-logic digital-analogue interfaces for accurate mixed-signal simulation
A new approach to mixed-signal circuit interfacing based on fuzzy logic models is presented. Due to their continuous rather than discrete character, fuzzy logic models offer a sig...
Tom J. Kazmierski
VTS
1996
IEEE
126views Hardware» more  VTS 1996»
14 years 2 months ago
Automatic test generation using genetically-engineered distinguishing sequences
A fault-oriented sequential circuit test generator is described in which various types of distinguishing sequences are derived, both statically and dynamically, to aid the test ge...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...