148 search results - page 12 / 30 » Improving simulation-based verification by means of formal m... |
MICRO
2008
IEEE
13 years 7 months ago
2008
IEEE
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
SAC
2010
ACM
13 years 5 months ago
2010
ACM
Verification conditions (VCs) are logical formulae whose validity implies the correctness of a program with respect to a specification. The technique of checking software properti...
AIME
2003
Springer
13 years 11 months ago
2003
Springer
Abstract. Medical practice protocols or guidelines are statements to assist practitioners and patient decisions about appropriate health care for specific circumstances. In order t...
JDCTA
2010
13 years 2 months ago
2010
Soundness and coercion resistance are the important and intricate security requirements for remote voting protocols. Several formal models of soundness and coercion-resistance hav...
IEE
2008
13 years 7 months ago
2008
ion techniques are indispensable for the specification and verification of functional behavior of programs. In object-oriented ation languages like JML, a powerful abstraction tec...