873 search results - page 47 / 175 » Improving the Effectiveness of Web Caching |
ASPLOS
1994
ACM
14 years 2 months ago
1994
ACM
In the past decade, processor speed has become significantly faster than memory speed. Small, fast cache memories are designed to overcome this discrepancy, but they are only effe...
IEEEPACT
2008
IEEE
14 years 4 months ago
2008
IEEE
Both commercial and scientific workloads benefit from concurrency and exhibit data sharing across threads/processes. The resulting sharing patterns are often fine-grain, with t...
HPCA
2005
IEEE
14 years 10 months ago
2005
IEEE
The memory system's large and growing contribution to system performance motivates more aggressive approaches to improving its efficiency. We propose and analyze a memory hie...
JSA
2010
13 years 8 months ago
2010
— Effective address calculation for load and store instructions needs to compete for ALU with other instructions and hence extra latencies might be incurred to data cache accesse...
LCTRTS
1999
Springer
14 years 2 months ago
1999
Springer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...