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HPCA
2009
IEEE
16 years 6 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
DCOSS
2008
Springer
15 years 7 months ago
Time Synchronization in Heterogeneous Sensor Networks
Heterogeneous sensor networks consisting of resource-constrained nodes as well as resource-intensive nodes equipped with high-bandwidth sensors offer significant advantages for dev...
Isaac Amundson, Branislav Kusy, Péter V&oum...
ISCA
1998
IEEE
134views Hardware» more  ISCA 1998»
15 years 10 months ago
Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor
Much of the improvement in computer performance over the last twenty years has come from faster transistors and architectural advances that increase parallelism. Historically, par...
Stephen W. Keckler, William J. Dally, Daniel Maski...
EMNLP
2007
15 years 7 months ago
Structured Prediction Models via the Matrix-Tree Theorem
This paper provides an algorithmic framework for learning statistical models involving directed spanning trees, or equivalently non-projective dependency structures. We show how p...
Terry Koo, Amir Globerson, Xavier Carreras, Michae...
CCGRID
2003
IEEE
15 years 11 months ago
Discretionary Caching for I/O on Clusters
I/O bottlenecks are already a problem in many largescale applications that manipulate huge datasets. This problem is expected to get worse as applications get larger, and the I/O ...
Murali Vilayannur, Anand Sivasubramaniam, Mahmut T...