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VL
1995
IEEE
13 years 11 months ago
1995
IEEE
Buffering of intermediate results in dataflow diagrams can significantly reduce latency when a user browses these results or re-executes a diagram with slightly different inputs. ...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...
PIMRC
2010
IEEE
13 years 5 months ago
2010
IEEE
In this paper, a new type of collaboration in wireless sensor networks (WSN) is suggested that exploits array processing algorithms for better reception of a signal. For receive co...
ICASSP
2011
IEEE
12 years 11 months ago
2011
IEEE
Owing to the non-zero probability of the missed detection and false alarm of active primary transmission, a certain degree of performance degradation of the primary user (PU) from...
DAC
2004
ACM
14 years 9 months ago
2004
ACM
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...