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APCSAC
2001
IEEE
15 years 9 months ago
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
Kenji Watanabe, Wanming Chu, Yamin Li
BIBE
2001
IEEE
15 years 9 months ago
Gene Classification using Expression Profiles: A Feasibility Study
As various genome sequencing projects have already been completed or are near completion, genome researchers are shifting their focus from structural genomics to functional genomi...
Michihiro Kuramochi, George Karypis
FPGA
2000
ACM
122views FPGA» more  FPGA 2000»
15 years 9 months ago
A reconfigurable multi-function computing cache architecture
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
Huesung Kim, Arun K. Somani, Akhilesh Tyagi
IFIP
2000
Springer
15 years 9 months ago
Process as Theory in Information Systems Research
Many researchers have searched for evidence of organizational improvements from the huge sums invested in ICT. Unfortunately, evidence for such a pay back is spotty at best (e.g.,...
Kevin Crowston
ISCA
2000
IEEE
93views Hardware» more  ISCA 2000»
15 years 9 months ago
Reconfigurable caches and their application to media processing
High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing...
Parthasarathy Ranganathan, Sarita V. Adve, Norman ...
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