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ICCAD
2005
IEEE
130views Hardware» more  ICCAD 2005»
14 years 5 months ago
A cache-defect-aware code placement algorithm for improving the performance of processors
— Yield improvement through exploiting fault-free sections of defective chips is a well-known technique [1][2]. The idea is to partition the circuitry of a chip in a way that fau...
Tohru Ishihara, Farzan Fallah
CORR
2010
Springer
167views Education» more  CORR 2010»
13 years 8 months ago
Performance Analysis of an Improved Graded Precision Localization Algorithm for Wireless Sensor Networks
In this paper an improved version of the graded precision localization algorithm GRADELOC, called IGRADELOC is proposed. The performance of GRADELOC is dependent on the regions fo...
Sanat Sarangi, Subrat Kar
IJIT
2004
13 years 10 months ago
Restartings: A Technique to Improve Classic Genetic Algorithms' Performance
In this contribution, a way to enhance the performance of the classic Genetic Algorithm is proposed. The idea of restarting a Genetic Algorithm is applied in order to obtain better...
Grigorios N. Beligiannis, Georgios A. Tsirogiannis...
IJCSA
2008
137views more  IJCSA 2008»
13 years 8 months ago
Algorithms to Improve Performance of Natural Language Interface
: Performance of Natural Language Interface often deteriorates due to linguistic phenomena of Semantic Symmetry and Ambiguous Modification (Katz and Lin, 2003). In this paper we pr...
M. R. Joshi, R. A. Akerkar
GECCO
2009
Springer
192views Optimization» more  GECCO 2009»
13 years 6 months ago
Improving SMT performance: an application of genetic algorithms to configure resizable caches
Simultaneous Multithreading (SMT) is a technology aimed at improving the throughput of the processor core by applying Instruction Level Parallelism (ILP) and Thread Level Parallel...
Josefa Díaz, José Ignacio Hidalgo, F...