Sciweavers

164 search results - page 13 / 33
» Improving the performance of hypervisor-based fault toleranc...
Sort
View
ISCA
2012
IEEE
320views Hardware» more  ISCA 2012»
11 years 11 months ago
Viper: Virtual pipelines for enhanced reliability
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...
Andrea Pellegrini, Joseph L. Greathouse, Valeria B...
DATE
2000
IEEE
90views Hardware» more  DATE 2000»
14 years 28 days ago
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
Lorena Anghel, Michael Nicolaidis
CORR
2008
Springer
150views Education» more  CORR 2008»
13 years 8 months ago
A Dynamic Programming Framework for Combinatorial Optimization Problems on Graphs with Bounded Pathwidth
In this paper we present an algorithmic framework for solving a class of combinatorial optimization problems on graphs with bounded pathwidth. The problems are NP-hard in general, ...
Mugurel Ionut Andreica
SIGSOFT
2008
ACM
14 years 9 months ago
Experimenting with exception propagation mechanisms in service-oriented architecture
Exception handling is one of the popular means used for improving dependability and supporting recovery in the ServiceOriented Architecture (SOA). This practical experience paper ...
Anatoliy Gorbenko, Alexander Romanovsky, Vyachesla...
ICCD
2003
IEEE
113views Hardware» more  ICCD 2003»
14 years 5 months ago
Exploiting Microarchitectural Redundancy For Defect Tolerance
Continued advancements in fabrication technology and reductions in feature size create challenges in maintaining both manufacturing yield rates and long-term reliability of device...
Premkishore Shivakumar, Stephen W. Keckler, Charle...