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ICES
2003
Springer
112views Hardware» more  ICES 2003»
14 years 18 days ago
Using Negative Correlation to Evolve Fault-Tolerant Circuits
In this paper, we show how artificial evolution can be used to improve the fault-tolerance of electronic circuits. We show that evolution is able to improve the fault tolerance of...
Thorsten Schnier, Xin Yao
DSN
2007
IEEE
14 years 1 months ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...
TDSC
2010
101views more  TDSC 2010»
13 years 5 months ago
Steward: Scaling Byzantine Fault-Tolerant Replication to Wide Area Networks
—This paper presents the first hierarchical Byzantine fault-tolerant replication architecture suitable to systems that span multiple wide area sites. The architecture confines ...
Yair Amir, Claudiu Danilov, Danny Dolev, Jonathan ...
HPCC
2007
Springer
14 years 1 months ago
Improving a Fault-Tolerant Routing Algorithm Using Detailed Traffic Analysis
Currently, some coarse measures like global network latency are used to compare routing protocols. These measures do not provide enough insight of traffic distribution among networ...
Abbas Nayebi, Arash Shamaei, Hamid Sarbazi-Azad
TC
1998
13 years 7 months ago
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
—The very high levels of integration and submicron device sizes used in current and emerging VLSI technologies for FPGAs lead to higher occurrences of defects and operational fau...
Fran Hanchek, Shantanu Dutt