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» Improving yield and reliability of chip multiprocessors
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TC
2010
13 years 6 months ago
PERFECTORY: A Fault-Tolerant Directory Memory Architecture
—The number of CPUs in chip multiprocessors is growing at the Moore’s Law rate, due to continued technology advances. However, new technologies pose serious reliability challen...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
ICCAD
2007
IEEE
91views Hardware» more  ICCAD 2007»
14 years 4 months ago
Variation-aware task allocation and scheduling for MPSoC
— As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. As a result, a paradigm shift from determ...
Feng Wang 0004, Chrysostomos Nicopoulos, Xiaoxia W...
ASAP
2008
IEEE
142views Hardware» more  ASAP 2008»
14 years 2 months ago
Managing multi-core soft-error reliability through utility-driven cross domain optimization
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
Wangyuan Zhang, Tao Li
DAC
2010
ACM
13 years 11 months ago
Performance yield-driven task allocation and scheduling for MPSoCs under process variation
With the ever-increasing transistor variability in CMOS technology, it is essential to integrate variation-aware performance analysis into the task allocation and scheduling proce...
Lin Huang, Qiang Xu
TCAD
2008
119views more  TCAD 2008»
13 years 7 months ago
Full-Chip Routing Considering Double-Via Insertion
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, ...
Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lum...