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SAS
2007
Springer
108views Formal Methods» more  SAS 2007»
14 years 3 months ago
Programming Language Design and Analysis Motivated by Hardware Evolution
Abstract. Silicon chip design has passed a threshold whereby exponentially increasing transistor density (Moore’s Law) no longer translates into increased processing power for si...
Alan Mycroft
MICRO
1998
IEEE
79views Hardware» more  MICRO 1998»
14 years 1 months ago
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...
David López, Josep Llosa, Mateo Valero, Edu...
ISVLSI
2002
IEEE
89views VLSI» more  ISVLSI 2002»
14 years 2 months ago
Speedup of Self-Timed Digital Systems Using Early Completion
An Early Completion technique is developed to significantly increase the throughput of NULL Convention self-timed digital systems without impacting latency or compromising their s...
Scott C. Smith
ITC
1996
IEEE
107views Hardware» more  ITC 1996»
14 years 1 months ago
Orthogonal Scan: Low-Overhead Scan for Data Paths
Orthogonal scan paths, which follow the path of the data flow, can be used in data path designs to reduce the test overhead -- area, delay and test application time -- by sharing ...
Robert B. Norwood, Edward J. McCluskey
ISSS
2002
IEEE
103views Hardware» more  ISSS 2002»
14 years 2 months ago
A Symbolic Approach for the Combined Solution of Scheduling and Allocation
Scheduling is widely recognized as a very important step in highlevel synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware im...
Luciano Lavagno, Mihai T. Lazarescu, Stefano Quer,...