122 search results - page 8 / 25 » In Situ Design of Register Operations |
CATA
2004
13 years 11 months ago
2004
This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is co...
TACAS
2007
Springer
14 years 3 months ago
2007
Springer
This paper presents a mechanised Hoare-style programming logic framework for assembly level programs. The framework has been designed to fit on top of operational semantics of rea...
ASPDAC
2005
ACM
14 years 3 months ago
2005
ACM
- Many high-level description languages, such as C/C++ or Java, lack the capability to specify the bitwidth information for variables and operations. Synthesis from these specifica...
VLSID
2007
IEEE
14 years 10 months ago
2007
IEEE
Performance of an application can be improved through augmenting the processor with Application specific Functional Units (AFUs). Usually a cluster of operations identified from th...
FPGA
2004
ACM
14 years 3 months ago
2004
ACM
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...