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137
Voted
DAC
1997
ACM
15 years 7 months ago
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures
—Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexe...
Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas
141
Voted
FSE
2005
Springer
153views Cryptology» more  FSE 2005»
15 years 9 months ago
F-FCSR: Design of a New Class of Stream Ciphers
In this paper we present a new class of stream ciphers based on a very simple mechanism. The heart of our method is a Feedback with Carry Shift Registers (FCSR) automaton. This au...
François Arnault, Thierry P. Berger
139
Voted
PPOPP
2003
ACM
15 years 9 months ago
Impala: a middleware system for managing autonomic, parallel sensor systems
Sensor networks are long-running computer systems with many sensing/compute nodes working to gather information about their environment, process and fuse that information, and in ...
Ting Liu, Margaret Martonosi
148
Voted
CF
2009
ACM
15 years 10 months ago
Mapping the LU decomposition on a many-core architecture: challenges and solutions
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
Ioannis E. Venetis, Guang R. Gao
134
Voted
CODES
2007
IEEE
15 years 10 months ago
A low power VLIW processor generation method by means of extracting non-redundant activation conditions
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuc...