A low power VLIW processor generation method by means of extracting non-redundant activation conditions

This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is important for the best power reduction by clock gating to create control signals that can completely shut off redundant clock supplies for registers. In order to generate the control signals automatically, the proposed method utilizes highlevel architecture information called Micro-Operation Descriptions, which describes a VLIW processor architecture. Exploiting the Micro-Operation Descriptions in a VLIW processor generation process, the proposed method automatically extracts the non-redundant activation conditions that can control clock gating to supply the minimum clocks to the pipeline registers. Using the non-redundant activation condition extraction, the proposed method achieves short calculation time and low area overhead; the proposed method can be applied to VLIW processor generation. Experimental result...

• Type: Conference
• Year: 2007
• Where: CODES
• Authors: Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
• Keywords: Clock Gating, CODES 2007, Hardware-Software Codesign, VLIW Processor, VLIW Processor Generation