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TPDS
2010
125views more  TPDS 2010»
13 years 2 months ago
Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level
The importance of transient faults is predicted to grow due to current technology trends of increased scale of integration. One of the components that will be significantly affecte...
Ricardo Fernández Pascual, José M. G...
CHARME
2001
Springer
162views Hardware» more  CHARME 2001»
13 years 11 months ago
Parameterized Verification of the FLASH Cache Coherence Protocol by Compositional Model Checking
We consider the formal verification of the cache coherence protocol of the Stanford FLASH multiprocessor for N processors. The proof uses the SMV proof assistant, a proof system ba...
Kenneth L. McMillan
NOCS
2007
IEEE
14 years 1 months ago
The Power of Priority: NoC Based Distributed Cache Coherency
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginos...
TC
2011
13 years 2 months ago
Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom Filters
— Implementing shared memory consistency models on top of hardware caches gives rise to the well-known cache coherence problem. The standard solution involves implementing cohere...
Thomas J. Ashby, Pedro Diaz, Marcelo Cintra
DSN
2008
IEEE
14 years 2 months ago
A fault-tolerant directory-based cache coherence protocol for CMP architectures
Current technology trends of increased scale of integration are pushing CMOS technology into the deepsubmicron domain, enabling the creation of chips with a significantly greater...
Ricardo Fernández Pascual, José M. G...