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IEEEPACT
2005
IEEE
14 years 1 months ago
Characterization of TCC on Chip-Multiprocessors
Transactional Coherence and Consistency (TCC) is a novel coherence scheme for shared memory multiprocessors that uses programmer-defined transactions as the fundamental unit of p...
Austen McDonald, JaeWoong Chung, Hassan Chafi, Chi...
IPPS
1997
IEEE
13 years 11 months ago
View Caching: Efficient Software Shared Memory for Dynamic Computations
Software distributed shared memory (DSM) techniques, while effective on applications with coarse-grained sharing, yield poor performance for the fine-grained sharing encountered i...
Vijay Karamcheti, Andrew A. Chien
MICRO
2006
IEEE
117views Hardware» more  MICRO 2006»
14 years 1 months ago
Coherence Ordering for Ring-based Chip Multiprocessors
Ring interconnects may be an attractive solution for future chip multiprocessors because they can enable faster links than buses and simpler switches than arbitrary switched inter...
Michael R. Marty, Mark D. Hill
ACTA
2006
108views more  ACTA 2006»
13 years 7 months ago
Refinement verification of the lazy caching algorithm
The lazy caching algorithm of Afek, Brown, and Merrit (1993) is a protocol that allows the use of local caches with delayed updates. It results in a memory model that is not atomi...
Wim H. Hesselink
IEEEPACT
2009
IEEE
14 years 2 months ago
DDCache: Decoupled and Delegable Cache Data and Metadata
Abstract—In order to harness the full compute power of manycore processors, future designs must focus on effective utilization of on-chip cache and bandwidth resources. In this p...
Hemayet Hossain, Sandhya Dwarkadas, Michael C. Hua...