309 search results - page 36 / 62 » In-Network Cache Coherence |
HPCA
1998
IEEE
13 years 12 months ago
1998
IEEE
Run-time parallelization is often the only way to execute the code in parallel when data dependence information is incomplete at compile time. This situation is common in many imp...
RT
1997
Springer
13 years 11 months ago
1997
Springer
Abstract. This paper proposes a simple augmentation to texture mapping hardware which produces the correct depth buffer content and hence correct visibility when replacing complex ...
ASPLOS
1996
ACM
13 years 11 months ago
1996
ACM
This paper describes Shasta, a system that supports a shared address space in software on clusters of computers with physically distributed memory. A unique aspect of Shasta compa...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
We describe a technique for verifying that a hardware design correctly implements a protocol-level formal specification. Simulation steps are translated to protocol state transiti...
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
There are two basic models for the on-chip memory in CMP systems: hardware-managed coherent caches and software-managed streaming memory. This paper performs a direct comparison o...