309 search results - page 45 / 62 » In-Network Cache Coherence |
SIGGRAPH
1997
ACM
13 years 11 months ago
1997
ACM
Simulating realistic lighting and rendering complex scenes are usually considered separate problems with incompatible solutions. Accurate lighting calculations are typically perfo...
MICRO
2010
IEEE
13 years 6 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
IEEEPACT
2003
IEEE
14 years 27 days ago
2003
IEEE
This paper presents a framework for analyzing the performance of multithreaded programs using a model called a constraint graph. We review previous constraint graph definitions fo...
ISCA
1996
IEEE
13 years 11 months ago
1996
IEEE
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
SIGMETRICS
1996
ACM
13 years 11 months ago
1996
ACM
A large and increasing gap exists between processor and memory speeds in scalable cache-coherent multiprocessors. To cope with this situation, programmers and compiler writers mus...