309 search results - page 5 / 62 » In-Network Cache Coherence |
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
ISCA
2011
IEEE
12 years 11 months ago
2011
IEEE
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...
ICPADS
1994
IEEE
13 years 11 months ago
1994
IEEE
: Software cache coherence schemes are very desirable in the design of scalable multiprocessors and massively parallel processors. The authors propose a software cache coherence sc...
WMPI
2004
ACM
14 years 1 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
CODES
2009
IEEE
14 years 8 days ago
2009
IEEE
In a multiprocessor system-on-chip (MPSoC) private caches introduce the cache coherence problem. Here, we target at heterogeneous MPSoCs with a network-on-chip (NoC). Existing har...