Sciweavers

309 search results - page 60 / 62
» In-Network Cache Coherence
Sort
View
ISCA
2008
IEEE
134views Hardware» more  ISCA 2008»
14 years 2 months ago
Flexible Decoupled Transactional Memory Support
A high-concurrency transactional memory (TM) implementation needs to track concurrent accesses, buffer speculative updates, and manage conflicts. We present a system, FlexTM (FLE...
Arrvindh Shriraman, Sandhya Dwarkadas, Michael L. ...
ASPLOS
2006
ACM
14 years 1 months ago
AVIO: detecting atomicity violations via access interleaving invariants
Concurrency bugs are among the most difficult to test and diagnose of all software bugs. The multicore technology trend worsens this problem. Most previous concurrency bug detect...
Shan Lu, Joseph Tucek, Feng Qin, Yuanyuan Zhou
SPAA
2006
ACM
14 years 1 months ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
PLDI
2010
ACM
14 years 19 days ago
Adversarial memory for detecting destructive races
Multithreaded programs are notoriously prone to race conditions, a problem exacerbated by the widespread adoption of multi-core processors with complex memory models and cache coh...
Cormac Flanagan, Stephen N. Freund
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
14 years 14 days ago
Tarantula: A Vector Extension to the Alpha Architecture
Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processo...
Roger Espasa, Federico Ardanaz, Julio Gago, Roger ...