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ICPP
1996
IEEE
13 years 11 months ago
A Timestamp-based Selective Invalidation Scheme for Multiprocessor Cache Coherence
- Among all software cache coherence strategaes, the ones that are based on the concept of tamestamps show the greatest potentaal an terms of cache performance. The early tamestamp...
Xin Yuan, Rami G. Melhem, Rajiv Gupta
DAC
2005
ACM
14 years 8 months ago
Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs
We propose two novel integration techniques -- bypass and bookkeeping -- in the memory controller to address the cache coherence compatibility issue of a non-shared bus heterogene...
Taeweon Suh, Daehyun Kim, Hsien-Hsin S. Lee
POS
1998
Springer
13 years 11 months ago
The Transactional Object Cache: A Foundation for High Performance Persistent System Construction
This paper argues that caching, atomicity and layering are fundamental to persistent systems, and that the transactional object cache architecture, as an embodiment of these conce...
Stephen Blackburn, Robin Stanton
CODES
2008
IEEE
14 years 2 months ago
Extending open core protocol to support system-level cache coherence
Open Core Protocol (OCP) is a standard on-chip core interface specification. The current release is flexible and configurable to support the communication needs of a wide range...
Konstantinos Aisopos, Chien-Chun Chou, Li-Shiuan P...
CHARME
2003
Springer
110views Hardware» more  CHARME 2003»
13 years 11 months ago
Exact and Efficient Verification of Parameterized Cache Coherence Protocols
Abstract. We propose new, tractably (in some cases provably) efficient algorithmic methods for exact (sound and complete) parameterized reasoning about cache coherence protocols. F...
E. Allen Emerson, Vineet Kahlon