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» Increasing Pipelined IP Core Utilization in Process Networks...
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SLIP
2006
ACM
14 years 20 days ago
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...
FPL
2004
Springer
171views Hardware» more  FPL 2004»
14 years 2 days ago
A Modular System for FPGA-Based TCP Flow Processing in High-Speed Networks
Field Programmable Gate Arrays (FPGAs) can be used in Intrusion Prevention Systems (IPS) to inspect application data contained within network flows. An IPS operating on high-speed...
David V. Schuehler, John W. Lockwood
INFOCOM
2009
IEEE
14 years 1 months ago
Nuclei: GPU-Accelerated Many-Core Network Coding
—While it is a well known result that network coding achieves optimal flow rates in multicast sessions, its potential for practical use has remained to be a question, due to its...
Hassan Shojania, Baochun Li, Xin Wang
ISCAS
2006
IEEE
74views Hardware» more  ISCAS 2006»
14 years 22 days ago
NIUGAP: low latency network interface architecture with Gray code for networks-on-chip
— The implementation of a high-performance network-on-chip (NoC) requires an efficient design for the network interface unit (NIU) that connects the switched network to the IP c...
Daewook Kim, Manho Kim, Gerald E. Sobelman
APSCC
2008
IEEE
14 years 1 months ago
Integration and Implementation of Secured IP Based Surveillance Networks
— This paper presents a method of integration and implementation of transmitting video and audio data from multiple Internet Protocol (IP) surveillance cameras in a wireless sens...
Charles C. Castello, Jeffrey Fan, Te-Shun Chou, Ho...