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» Increasing Pipelined IP Core Utilization in Process Networks...
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MICRO
2008
IEEE
139views Hardware» more  MICRO 2008»
14 years 1 months ago
Adaptive data compression for high-performance low-power on-chip networks
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...
Yuho Jin, Ki Hwan Yum, Eun Jung Kim
NETWORK
2007
100views more  NETWORK 2007»
13 years 6 months ago
Parallel Programmable Ethernet Controllers: Performance and Security
Programmable network interfaces can provide network servers with a flexible interface to high-bandwidth Ethernet links, but they face critical software and architectural challenge...
Derek L. Schuff, Vijay S. Pai, Paul Willmann, Scot...
ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
13 years 5 months ago
Evolution of thread-level parallelism in desktop applications
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mu...
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
14 years 9 days ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
INFOCOM
2005
IEEE
14 years 9 days ago
Practical routing-layer support for scalable multihoming
— The recent trend of rapid increase in routing table sizes at routers comprising the Internet’s core is posing a serious challenge to the current Internet’s scalability, ava...
Ramakrishna Gummadi, Ramesh Govindan