661 search results - page 108 / 133 » Increasing Processor Performance by Implementing Deeper Pipe... |
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Dual-execution/checkpointing based transient error tolerance techniques have been widely used in the high-end mission critical systems. These techniques, however, are not very att...
ICFP
2007
ACM
14 years 7 months ago
2007
ACM
In the light of evidence that Haskell programs compiled by GHC exhibit large numbers of mispredicted branches on modern processors, we re-examine the "tagless" aspect of...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access ...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
Multiple programming models are emerging to address an increased need for dynamic task parallelism in applications for multicore processors and shared-address-space parallel compu...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...