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IPPS
2007
IEEE
14 years 1 months ago
Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions
Parallel processing using multiple processors is a well-established technique to accelerate many different classes of applications. However, as the density of chips increases, ano...
Colin J. Ihrig, Justin Stander, Alex K. Jones
IEEEPACT
2007
IEEE
14 years 1 months ago
Speculative Decoupled Software Pipelining
In recent years, microprocessor manufacturers have shifted their focus from single-core to multi-core processors. To avoid burdening programmers with the responsibility of paralle...
Neil Vachharajani, Ram Rangan, Easwaran Raman, Mat...
DAC
1999
ACM
13 years 11 months ago
Dynamically Reconfigurable Architecture for Image Processor Applications
This work presents an overview of the principles that underlie the speed-up achievable by dynamic hardware reconfiguration, proposes a more precise taxonomy for the execution mode...
Alexandro M. S. Adário, Eduardo L. Roehe, S...
HPDC
1999
IEEE
13 years 11 months ago
Using Embedded Network Processors to Implement Global Memory Management in a Workstation Cluster
Advances in network technology continue to improve the communication performance of workstation and PC clusters, making high-performance workstation-clustercomputing increasingly ...
Yvonne Coady, Joon Suan Ong, Michael J. Feeley
SIGARCH
2008
94views more  SIGARCH 2008»
13 years 7 months ago
Optimized on-chip pipelining of memory-intensive computations on the cell BE
Multiprocessors-on-chip, such as the Cell BE processor, regularly suffer from restricted bandwidth to off-chip main memory. We propose to reduce memory bandwidth requirements, and...
Christoph W. Kessler, Jörg Keller