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PLDI
1995
ACM
13 years 11 months ago
Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
Jack L. Lo, Susan J. Eggers
DAC
2011
ACM
12 years 7 months ago
EFFEX: an embedded processor for computer vision based feature extraction
The deployment of computer vision algorithms in mobile applications is growing at a rapid pace. A primary component of the computer vision software pipeline is feature extraction,...
Jason Clemons, Andrew Jones, Robert Perricone, Sil...
ICIP
2007
IEEE
14 years 1 months ago
Software Pipelines Design for Variable Block-Size Motion Estimation with Large Search Range
This paper presents some techniques for efficient motion estimation (ME) implementation on fixed-point digital signal processor (DSP) for high resolution video coding. First, chal...
Zhigang Yang, Wen Gao, Yan Liu, Debin Zhao
IEEEPACT
2006
IEEE
14 years 1 months ago
Adaptive reorder buffers for SMT processors
In SMT processors, the complex interplay between private and shared datapath resources needs to be considered in order to realize the full performance potential. In this paper, we...
Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev
EUC
2006
Springer
13 years 11 months ago
Saving Register-File Leakage Power by Monitoring Instruction Sequence in ROB
- Modern portable or embedded systems support more and more complex applications. These applications make embedded devices require not only low powerconsumption, but also high comp...
Wann-Yun Shieh, Hsin-Dar Chen