Sciweavers

1139 search results - page 213 / 228
» Increasing the throughput of HomePNA
Sort
View
CODES
2005
IEEE
14 years 4 months ago
Aggregating processor free time for energy reduction
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
ICDCS
2005
IEEE
14 years 4 months ago
End-to-End Fair Bandwidth Allocation in Multi-Hop Wireless Ad Hoc Networks
— The shared-medium multi-hop nature of wireless ad hoc networks poses fundamental challenges to the design of an effective resource allocation algorithm to maximize spatial reus...
Baochun Li
ICDCS
2005
IEEE
14 years 4 months ago
Handling Asymmetry in Power Heterogeneous Ad Hoc Networks: A Cross Layer Approach
Power heterogeneous ad hoc networks are characterized by link layer asymmetry: the ability of lower power nodes to receive transmissions from higher power nodes but not vice versa...
Vasudev Shah, Srikanth V. Krishnamurthy
INFOCOM
2005
IEEE
14 years 4 months ago
A QoS-aware AIMD protocol for time-sensitive applications in wired/wireless networks
Abstract— A TCP-friendly Additive Increase and Multiplicative Decrease (AIMD) protocol is proposed to support timesensitive applications in hybrid wired/wireless networks. By ana...
Lin Cai, Xuemin Shen, Jon W. Mark, Jianping Pan
ISCA
2005
IEEE
119views Hardware» more  ISCA 2005»
14 years 4 months ago
Rescue: A Microarchitecture for Testability and Defect Tolerance
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
Ethan Schuchman, T. N. Vijaykumar