54 search results - page 9 / 11 » Incremental Circuit Simulation Using Waveform Relaxation |
TCAD
2008
13 years 7 months ago
2008
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
- This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-sca...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
Extracting the inductance of complex interconnect topologies is a formidable task, and simulating the resulting dense partial inductance matrix is even more difficult. Furthermore...