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FPGA
2005
ACM
80views FPGA» more  FPGA 2005»
14 years 3 months ago
Simultaneous timing-driven placement and duplication
Logic duplication is an effective method for improving circuit performance. In this paper we present an algorithm named SPD that performs simultaneous placement and duplication to...
Gang Chen, Jason Cong
NDSS
2000
IEEE
14 years 2 months ago
Secure Border Gateway Protocol (S-BGP) - Real World Performance and Deployment Issues
The Border Gateway Protocol (BGP), which is used to distribute routing information between autonomous systems, is an important component of the Internet’s routing infrastructure...
Stephen T. Kent, Charles Lynn, Joanne Mikkelson, K...
FPGA
2004
ACM
126views FPGA» more  FPGA 2004»
14 years 3 months ago
A synthesis oriented omniscient manual editor
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
Tomasz S. Czajkowski, Jonathan Rose
DAC
2009
ACM
14 years 10 months ago
Handling complexities in modern large-scale mixed-size placement
In this paper, we propose an effective algorithm flow to handle largescale mixed-size placement. The basic idea is to use floorplanning to guide the placement of objects at the gl...
Jackey Z. Yan, Natarajan Viswanathan, Chris Chu
ISPD
2010
ACM
217views Hardware» more  ISPD 2010»
14 years 4 months ago
ITOP: integrating timing optimization within placement
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...
Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy,...