452 search results - page 15 / 91 » Incremental formal design verification |
CADE
2002
Springer
14 years 7 months ago
2002
Springer
This paper reports on the formal proof of correctness of a compiler from a substantial subset of Java source language to Java bytecode in the proof environment Isabelle. This work ...
DAC
2006
ACM
14 years 1 months ago
2006
ACM
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
ISCAS
2003
IEEE
14 years 20 days ago
2003
IEEE
In modern System-on-Chip (SoC) designs verification becomes the major bottleneck. Since by using state-of-theart techniques complete designs cannot be fully formally verified, it ...
EUROMICRO
2004
IEEE
13 years 11 months ago
2004
IEEE
We illustrate a symbiotic relationship between existing model oriented specification techniques and web services. Through the formal re-design of a platform for mobile team collab...
JSA
2008
13 years 6 months ago
2008
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...