452 search results - page 19 / 91 » Incremental formal design verification |
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
POPL
2008
ACM
14 years 7 months ago
2008
ACM
Translation validation consists of transforming a program and a posteriori validating it in order to detect a modification of its semantics. This approach can be used in a verifie...
CACM
2010
13 years 7 months ago
2010
We report on the formal, machine-checked verification of microkernel from an abstract specification down to its C implementation. We assume correctness of compiler, assembly code,...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden a...
POPL
2010
ACM
14 years 4 months ago
2010
ACM
This paper presents a method for creating formally correct just-intime (JIT) compilers. The tractability of our approach is demonstrated through, what we believe is the first, ver...