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» Incremental formal design verification
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ICCAD
2002
IEEE
142views Hardware» more  ICCAD 2002»
14 years 4 months ago
SAT and ATPG: Boolean engines for formal hardware verification
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
Armin Biere, Wolfgang Kunz
CCS
2009
ACM
13 years 11 months ago
On voting machine design for verification and testability
We present an approach for the design and analysis of an electronic voting machine based on a novel combination of formal verification and systematic testing. The system was desig...
Cynthia Sturton, Susmit Jha, Sanjit A. Seshia, Dav...
PERCOM
2010
ACM
13 years 5 months ago
Towards automated verification of autonomous networks: A case study in self-configuration
In autonomic networks, the self-configuration of network entities is one of the most desirable properties. In this paper, we show how formal verification techniques can verify the ...
JaeSeung Song, Tiejun Ma, Peter R. Pietzuch
DAC
2008
ACM
14 years 8 months ago
Construction of concrete verification models from C++
C++ based verification methodologies are now emerging as the preferred method for SOC design. However most of the verification involving the C++ models are simulation based. The c...
Malay Haldar, Gagandeep Singh, Saurabh Prabhakar, ...
APAQS
2001
IEEE
13 years 11 months ago
Incremental Fault-Tolerant Design in an Object-Oriented Setting
With the increasing emphasis on dependability in complex, distributed systems, it is essential that system development can be done gradually and at different levels of detail. In ...
Einar Broch Johnsen, Olaf Owe, Ellen Munthe-Kaas, ...