452 search results - page 82 / 91 » Incremental formal design verification |
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
ESOP
2010
Springer
14 years 4 months ago
2010
Springer
Transient faults are single-shot hardware errors caused by high energy particles from space, manufacturing defects, overheating, and other sources. Such faults can be devastating f...
PRIMA
2009
Springer
14 years 1 months ago
2009
Springer
Human performance can seriously degrade under demanding tasks. To improve performance, agents can reason about the current state of the human, and give the most appropriate and eff...
ASPDAC
1998
ACM
13 years 11 months ago
1998
ACM
Binary decision diagrams (BDDs) have been shown to be a powerful tool in formal verification. Efficient BDD construction techniques become more important as the complexity of proto...
ICECCS
2007
IEEE
13 years 11 months ago
2007
IEEE
Parts of the CICS transaction processing system were modelled formally in the 1980s in a collaborative project between IBM Hursley Park and Oxford University Computing Laboratory....