42 search results - page 6 / 9 » Inductive interconnect width optimization for low power |
HPCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
DELTA
2006
IEEE
14 years 1 months ago
2006
IEEE
In high speed digital circuits, the inductive effect is more dominant compared to capacitive effect. In particular, as the technology is shrinking, the spacing between interconnec...
GECCO
2005
Springer
14 years 26 days ago
2005
Springer
Genetic Algorithms have worked fairly well for the VLSI cell placement problem, albeit with significant run times. Two parallel models for GA are presented for VLSI cell placemen...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
One of the main tasks in analog design is the sizing of the circuit parameters, such as transistor lengths and widths, in order to obtain optimal circuit performances, such as hig...
ISCAS
2008
IEEE
14 years 1 months ago
2008
IEEE
— Long distance, low data-rate UWB communication for sensor network applications requires a highly energy efficient transceiver combined with circuit and system-level optimizati...