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DFT
2003
IEEE
117views VLSI» more  DFT 2003»
14 years 3 months ago
Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
Sobeeh Almukhaizim, Yiorgos Makris
SNPD
2007
13 years 11 months ago
Parallel analysis of polymorphic viral code using automated deduction system
As malicious code has become more sophisticated and pervasive, faster and more effective system for forensics and prevention is important. Particularly, quick analysis of polymorp...
Ruo Ando
ICCSA
2009
Springer
14 years 4 months ago
Hybrid Hard/Soft Decode-and-Forward Relaying Protocol with Distributed Turbo Code
This paper proposes a hybrid hard/soft decode-and-forward (DF) relaying protocol with distributed turbo code (DTC), based on error detection in cooperative communications. In order...
Taekhoon Kim, Dong In Kim
BMCBI
2011
13 years 1 months ago
Proteinortho: Detection of (Co-)Orthologs in Large-Scale Analysis
Background: Orthology analysis is an important part of data analysis in many areas of bioinformatics such as comparative genomics and molecular phylogenetics. The ever-increasing ...
Marcus Lechner, Sven Findeiß, Lydia Steiner,...
DSN
2004
IEEE
14 years 1 months ago
FRTR: A Scalable Mechanism for Global Routing Table Consistency
This paper presents a scalable mechanism, Fast Routing Table Recovery (FRTR), for detecting and correcting route inconsistencies between neighboring BGP routers. The large size of...
Lan Wang, Daniel Massey, Keyur Patel, Lixia Zhang