Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code

We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check codes and duplication in order to not only perform error detection but also provide diagnosis and correction capabilities. Informed selection among the outputs of the original synthesized circuit and the outputs of a constrained-sharing resynthesized duplicate with parity check codes renders a low-cost fault tolerant design. Experimental results confirm the efficacy of the proposed method as a general solution for designing fault tolerant circuits.

• Type: Conference
• Year: 2003
• Where: DFT
• Authors: Sobeeh Almukhaizim, Yiorgos Makris
• Keywords: DFT 2003, Error Detection, Fault Tolerant Circuits, Hardware, Parity Check Codes