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ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
13 years 12 months ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi
VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
14 years 1 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl
EIT
2008
IEEE
14 years 2 months ago
Architectural support for securing application data in embedded systems
—The rapid growth and pervasive use of embedded systems makes it easier for an adversary to gain physical access to these devices to launch attacks and reverse engineer of the sy...
Olga Gelbart, Eugen Leontie, Bhagirath Narahari, R...
HIPC
2000
Springer
13 years 11 months ago
Meta-data Management System for High-Performance Large-Scale Scientific Data Access
Many scientific applications manipulate large amount of data and, therefore, are parallelized on high-performance computing systems to take advantage of their computational power a...
Wei-keng Liao, Xiaohui Shen, Alok N. Choudhary
ICCS
2005
Springer
14 years 1 months ago
Collecting and Exploiting Cache-Reuse Metrics
Abstract. The increasing gap of processor and main memory performance underlines the need for cache-optimizations, especially on memoryintensive applications. Tools which are able ...
Josef Weidendorfer, Carsten Trinitis