78 search results - page 8 / 16 » Instruction Cache Fetch Policies for Speculative Execution |
ESA
2001
Springer
14 years 3 days ago
2001
Springer
Suppose that a program makes a sequence of m accesses (references) to data blocks, the cache can hold k < m blocks, an access to a block in the cache incurs one time unit, and ...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
Fetching instructions from a set-associative cache in an embedded processor can consume a large amount of energy due to the tag checks performed. Recent proposals to address this ...
APCSAC
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper describes a new on-demand wakeup prediction policy for instruction cache leakage control that achieves better leakage savings than prior policies, and avoids the perform...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
Advanced Synchronization Facility (ASF) is an AMD64 hardware extension for lock-free data structures and transactional memory. It provides a speculative region that atomically exec...
CODES
2008
IEEE
14 years 2 months ago
2008
IEEE
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...