174 search results - page 10 / 35 » Instruction Fetch Mechanisms for Multipath Execution Process... |
ISCA
1997
IEEE
13 years 11 months ago
1997
IEEE
Superscalar processors currently have the potential to fetch multiple basic blocks per cycle by employing one of several recently proposed instruction fetch mechanisms. However, t...
DSN
2007
IEEE
14 years 1 months ago
2007
IEEE
A new approach is proposed that exploits repetition inherent in programs to provide low-overhead transient fault protection in a processor. Programs repeatedly execute the same in...
HPCA
2000
IEEE
13 years 12 months ago
2000
IEEE
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction, and executes speculatively its data-dependent instructions based on ...
ISCA
2003
IEEE
14 years 22 days ago
2003
IEEE
On a N-way issue superscalar processor, the front end instruction fetch engine must deliver instructions to the execution core at a sustained rate higher than N instructions per c...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...