174 search results - page 19 / 35 » Instruction Fetch Mechanisms for Multipath Execution Process... |
HPCA
2004
IEEE
14 years 7 months ago
2004
IEEE
Branch misprediction penalty consists of two components: the time wasted on mis-speculative execution until the mispredicted branch is resolved and the time to restart the pipelin...
ISCAPDCS
2003
13 years 8 months ago
2003
Branch predictors and processor front-ends have been the focus of a number of computer architecture studies. Typically they are evaluated separately from other components using tr...
ISLPED
1999
ACM
13 years 11 months ago
1999
ACM
In this paper, we propose a technique that uses an additional mini cache, the L0-Cache, located between the instruction cache I-Cache and the CPU core. This mechanism can provid...
ISCA
2012
IEEE
11 years 10 months ago
2012
IEEE
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
CAL
2006
13 years 7 months ago
2006
This paper makes a case for using multi-core processors to simultaneously achieve transient-fault tolerance and performance enhancement. Our approach is extended from a recent late...