Sciweavers

174 search results - page 4 / 35
» Instruction Fetch Mechanisms for Multipath Execution Process...
Sort
View
CASES
2001
ACM
13 years 11 months ago
Heads and tails: a variable-length instruction format supporting parallel fetch and decode
Abstract. Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and de...
Heidi Pan, Krste Asanovic
MICRO
1996
IEEE
129views Hardware» more  MICRO 1996»
13 years 11 months ago
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
Eric Rotenberg, Steve Bennett, James E. Smith
MICRO
1999
IEEE
115views Hardware» more  MICRO 1999»
13 years 11 months ago
Fetch Directed Instruction Prefetching
Instruction supply is a crucial component of processor performance. Instruction prefetching has been proposed as a mechanism to help reduce instruction cache misses, which in turn...
Glenn Reinman, Brad Calder, Todd M. Austin
CF
2004
ACM
14 years 27 days ago
Predictable performance in SMT processors
Current instruction fetch policies in SMT processors are oriented towards optimization of overall throughput and/or fairness. However, they provide no control over how individual ...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...
ISHPC
2003
Springer
14 years 19 days ago
Improving Memory Latency Aware Fetch Policies for SMT Processors
Abstract. In SMT processors several threads run simultaneously to increase available ILP, sharing but competing for resources. The instruction fetch policy plays a key role, determ...
Francisco J. Cazorla, Enrique Fernández, Al...