174 search results - page 5 / 35 » Instruction Fetch Mechanisms for Multipath Execution Process... |
IEEEPACT
1998
IEEE
13 years 11 months ago
1998
IEEE
Conventional speculative architectures use branch prediction to evaluate the most likely execution path during program execution. However, certain branches are difficult to predic...
HPCA
2007
IEEE
14 years 7 months ago
2007
IEEE
A thread executing on a simultaneous multithreading (SMT) processor that experiences a long-latency load will eventually stall while holding execution resources. Existing long-lat...
HIPEAC
2007
Springer
14 years 1 months ago
2007
Springer
In a dynamic reordering superscalar processor, the front-end fetches instructions and places them in the issue queue. Instructions are then issued by the back-end execution core. T...
HPCA
1999
IEEE
13 years 11 months ago
1999
IEEE
Processors that can simultaneously execute multiple paths of execution will only exacerbate the fetch bandwidth problem already plaguing conventional processors. On a multiple-pat...
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...