174 search results - page 7 / 35 » Instruction Fetch Mechanisms for Multipath Execution Process... |
EUROMICRO
1998
IEEE
13 years 11 months ago
1998
IEEE
In this paper we present a novel processor microarchitecture that relieves three of the most important bottlenecks of superscalar processors: the serialization imposed by true dep...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
Previous research has shown that the SPEC benchmarks achieve low miss ratios in relatively small instruction caches. This paper presents evidence that current software-development...
CAL
2005
13 years 7 months ago
2005
Previous research on runahead execution took it for granted as a prefetch-only technique. Even though the results of instructions independent of an L2 miss are correctly computed d...
IEEEPACT
2005
IEEE
14 years 1 months ago
2005
IEEE
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
GLVLSI
1998
IEEE
13 years 11 months ago
1998
IEEE
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...