174 search results - page 8 / 35 » Instruction Fetch Mechanisms for Multipath Execution Process... |
MICRO
1997
IEEE
13 years 11 months ago
1997
IEEE
We propose a method for compressing programs in embedded processors where instruction memory size dominates cost. A post-compilation analyzer examines a program and replaces commo...
ISPAN
2000
IEEE
13 years 12 months ago
2000
IEEE
We present new architectural concepts for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D2 -CPU (Data-Driven processor) follows the natura...
ISCA
2003
IEEE
14 years 22 days ago
2003
IEEE
As processor back-ends get more aggressive, front-ends will have to scale as well. Although the back-ends of superscalar processors have continued to become more parallel, the fro...
EUROPAR
2000
Springer
13 years 11 months ago
2000
Springer
Abstract This paper examines the behavior of current and next generation microprocessors' fetch engines while running Decision Support Systems (DSS) workloads. We analyze the ...
ICS
1999
Tsinghua U.
13 years 11 months ago
1999
Tsinghua U.
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...