Sciweavers

1192 search results - page 22 / 239
» Instruction Level Distributed Processing
Sort
View
IEEEPACT
2007
IEEE
14 years 1 months ago
Error Detection Using Dynamic Dataflow Verification
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
Albert Meixner, Daniel J. Sorin
ETS
2000
IEEE
121views Hardware» more  ETS 2000»
13 years 6 months ago
Increasing Access to Learning With Hybrid Audio-Data Collaboration
Internet enabled hybrid audio-data collaboration delivers high quality audio over telephone lines and data interaction over packet switched Internet connections, thus distributing...
Michael W. Freeman, Lawrence W. Grimes, J. Ray Hol...
IPPS
1997
IEEE
13 years 11 months ago
An Architecture Workbench for Multicomputers
The large design space of modern computer architectures calls for performance modelling tools to facilitate the evaluation of different alternatives. In this paper, we give an ove...
Andy D. Pimentel, Louis O. Hertzberger
APCSAC
2006
IEEE
14 years 25 days ago
A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster
In the ubiquitous era, it is necessary to research the architectures of multiprocessor system with high performance and low power consumption. A simulator developed in high level l...
Arata Shinozaki, Masatoshi Shima, Minyi Guo, Mitsu...
NN
2007
Springer
13 years 6 months ago
A neural model of decision-making by the superior colicullus in an antisaccade task
In the antisaccade paradigm subjects are instructed to perform eye movements in the opposite direction from the location of a visually appearing stimulus while they are fixating ...
Vassilis Cutsuridis, Nikolaos Smyrnis, Ioannis Evd...