1192 search results - page 5 / 239 » Instruction Level Distributed Processing |
DATE
2003
IEEE
13 years 12 months ago
2003
IEEE
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
HICSS
1994
IEEE
13 years 10 months ago
1994
IEEE
Our research goal is to design systems that enable humans to teach tedious, repetitive, simple tasks to a computer. We propose here a learner/problem solver architecture for such ...
FDL
2003
IEEE
13 years 12 months ago
2003
IEEE
The paper presents a methodology to integrate information on power consumption in a high level functional description of a System-on-chip. The power dissipated during the executio...
IEEEPACT
2002
IEEE
13 years 11 months ago
2002
IEEE
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper presents a new and retargetable method to identify patterns of instructions with direct support in coarsegrained processing elements (PEs). The method uses a three-addr...