2784 search results - page 104 / 557 » Instruction Level Parallelism |
108
Voted
EUROPAR
1997
Springer
15 years 6 months ago
1997
Springer
Abstract. The serialization constraints induced by the detection and enforcement of true data dependences have always been regarded as requirements for correct execution. We propos...
156
Voted
VLSID
2003
IEEE
2003
IEEE
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
16 years 3 months ago
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
100
Voted
ARC
2009
Springer
15 years 9 months ago
2009
Springer
The parallel branching program machine (PBM128) consists of 128 branching program machines (BMs) and a programmable interconnection. To represent logic functions on BMs, we use qua...
130
click to vote
CF
2006
ACM
15 years 6 months ago
2006
ACM
This paper presents our experience mapping OpenMP parallel programming model to the IBM Cyclops-64 (C64) architecture. The C64 employs a many-core-on-a-chip design that integrates...
104
Voted
CCGRID
2008
IEEE
15 years 9 months ago
2008
IEEE
