2784 search results - page 106 / 557 » Instruction Level Parallelism |
123
Voted
APCSAC
2006
IEEE
15 years 8 months ago
2006
IEEE
In the ubiquitous era, it is necessary to research the architectures of multiprocessor system with high performance and low power consumption. A simulator developed in high level l...
134
Voted
HPCA
2006
IEEE
15 years 8 months ago
2006
IEEE
Caches are very inefficiently utilized because not all the excess data fetched into the cache, to exploit spatial locality, is utilized. We define cache utilization as the percent...
115
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FASE
2000
Springer
15 years 6 months ago
2000
Springer
This paper discusses highly general mechanisms for specifying the refinement of a real-time system as a collection of lower level parallel components that preserve the timing and f...
105
Voted
ICCD
2001
IEEE
15 years 11 months ago
2001
IEEE
Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption ...
118
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GECCO
2008
Springer
15 years 3 months ago
2008
Springer
The realization of a control unit can be done using a complex circuitry or microprogramming. The latter may be considered as an alternative method of implementation of machine ins...