2784 search results - page 14 / 557 » Instruction Level Parallelism |
MICRO
2003
IEEE
14 years 3 months ago
2003
IEEE
Large instruction window processors achieve high performance by exposing large amounts of instruction level parallelism. However, accessing large hardware structures typically req...
RTAS
2008
IEEE
14 years 4 months ago
2008
IEEE
Instruction scratchpads have been previously suggested as a way to reduce the worst case execution time (WCET) of hard real-time programs without introducing the analysis issues p...
ICS
2004
Tsinghua U.
14 years 3 months ago
2004
Tsinghua U.
In contemporary out-of-order superscalar design, high IPC is mainly achieved by exposing high instruction level parallelism (ILP). Scaling issue window size can certainly provide ...
ISCA
2002
IEEE
14 years 2 months ago
2002
IEEE
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
ASAP
2004
IEEE
14 years 1 months ago
2004
IEEE
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...